Job Description

Title: Digital SERDES Architect

Location: San Jose, CA Onsite Full time

Experience Level: 6+ Years

Employment Type: Full-Time

About the Role

We are seeking a Digital SERDES Architect with 6+ years of experience in digital design and architecture for high-speed PHYs. The candidate will define the digital architecture, clocking schemes, and protocol integration for SERDES IPs, collaborating across analog and system domains to deliver robust, scalable designs.

Key Responsibilities

• Define and develop digital architecture for SERDES PHYs (PCS, adaptation, calibration logic, DFT).
• Implement RTL for critical digital sub-blocks and oversee synthesis/STA sign-off.
• Develop behavioral models (Verilog-A/AMS/SystemVerilog) for system-level validation.
• Drive digital verification strategy (UVM, assertions, coverage).
• Collaborate with analog and package teams to ensure seamless integration.
• Support post-silicon debug, firmware development, and system-level testing .

Qualifications

• 6+ years of hands-on digital design/architecture in SERDES or high-speed IP.
• Strong background in RTL coding, synthesis, STA, and low-power design techniques .
• Knowledge of protocol standards (PCIe Gen5/6, UCIe, CXL, Ethernet, DDR) .
• Familiarity with DFT, calibration algorithms, and adaptation logic .
• Proficiency in UVM/verification environments .
• MS/PhD in Electrical or Computer Engineering (preferred).

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